Currently, known methods of packaging image sensors (CMOS Image Sensors, CISs) include Chip Scale Package (CSP), Chip On Board (COB), and Flip Chip (FC).
CIS CSP is a wafer level packaging technique widely used in medium-end and low-end, low-resolution (2M pixels or less) image sensors at present. This packaging technique bonds a wafer level glass to a wafer and separates the image sensor chips in the wafer from each other by cofferdam, and then manufactures Ball Grid Array (BGA) after arranging wiring on the back side of the wafer in pad region of ground wafer by manufacturing pad surface or metal connected through silicon via (TSV) technique surrounding the inner side of the holes in pad or T shape metal contacted chip level packaging technique at the side of pad after dicing, and then individually sealed cavity image sensor unit is formed after dicing. Module assembled structure is formed by SMT method during back-end. However, there are the following significant issues with CSP packaging: 1. influence on product performance: thick supporting glass has a great influence on light absorption, refraction, reflection, and diffraction for image sensors, especially on products with small size pixels; 2. reliability: during subsequent SMT processes and environmental changes during operation of the products, thermal expansion coefficient differences between different components of the package structure and gas sealed in the cavity result in reliability issues; 3. massive investment, large pollution control requirement, long production cycle, highly cost per chip particularly for high resolution, large size image sensor product.
CIS COB is a chip level packaging technique currently used generally in high end, high resolution (5M pixels or more) image sensors. This packaging technique has the back surface of the grinded, diced chip bonded to pad on PCB using bonding metal wire, mounts and lens with IR glass are installed to form assembly module structure. However, CSP packaging has the following significant issues: 1. it is very difficult to control micro dust, super high level clean room is needed and the cost of manufacture and maintenance is high; 2. product design is customized, cycle is long, and flexibility is insufficient; 3. large scale production is difficult.
CIS FC is a chip level packaging technique recently developed for high end, high resolution (5M pixels or more) image sensors. This packaging technique has the ground and cut chip pad with completed metal bumps on pad directly connected to the PCB pad by having all the contact bumps connected with the pad by thermo-ultrasonic effect to form a package structure. Module assembled structure is formed by pad or solder balls outside the PCB employing SMT method during back end. But FC packaging has the following significant issues: 1. this package requires PCB substrate to have thermal expansion coefficient close to Si, which is expensive; 2. it is difficult to manufacture reliably, the requirement of thermo-ultrasonic of all the bumps and the consistency of the connections to the pad are high, and the bumps and pad are hard-connected and extended poorly; 3. it is difficult to control micro dust, the demand on process environment is high and the cost is high.
In summary, it is in urgent need of a packaging technology with low cost, high performance, and high reliability to achieve an ultrathin package structure for high resolution, large scale image sensors.